1. Field of the Invention
The present invention relates to package structures, and, more particularly, to a package structure and a method for fabricating the package structure.
2. Description of Related Art
Along with the progress of semiconductor packaging technologies, various package types have been developed for semiconductor devices. To improve electrical performances and save spaces, a plurality of packages can be vertically stacked on one another to form a package on package (PoP) structure. Such a packaging method allows merging of heterogeneous technologies in a system-in-package (SiP) so as to systematically integrate a plurality of electronic components having different functions, such as a memory, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an image application processor and so on, and therefore is applicable to various thin type electronic products.
Generally, to form a PoP structure, at least two packages are stacked on one another and electrically connected through a plurality of solder balls. However, as the packages tend to have smaller sizes and fine pitches, solder bridging easily occurs between the solder balls of the PoP structure, thus adversely affecting the product yield.
Accordingly, copper pillars are formed to achieve a stand-off effect so as to prevent solder bridging. FIGS. 1A and 1B are schematic cross-sectional views showing a method for fabricating a PoP structure 1 according to the prior art.
Referring to FIG. 1A, a first substrate 11 having a first surface 11a with a plurality of copper pillars 13 and a second surface 11b opposite to the first surface 11a is provided.
Referring to FIG. 1B, an electronic component 15 is disposed on the first surface 11a and electrically connected to the first substrate 11 in a flip-chip manner. Then, a second substrate 12 is stacked on the first substrate 11 through the copper pillars 13. In particular, the second substrate 12 is bonded to the copper pillars 13 of the first substrate 11 through a plurality of conductive elements 17. Each of the conductive elements 17 consists of a metal pillar 170 and a solder material 171 formed on the metal pillar 170. Subsequently, an encapsulant 16 is formed between the first surface 11a of the first substrate 11 and the second substrate 12.
However, since the copper pillars 13 are formed by electroplating, the size of the copper pillars 13 is difficult to control and the copper pillars 13 tend to have uneven heights. As such, a positional deviation easily occurs to the joints between the conductive elements 17 and the copper pillars 13 and hence a poor bonding easily occurs therebetween, thereby reducing the electrical performance and the product yield of the PoP structure 1.
Therefore, there is a need to provide a method for fabricating a package structure so as to overcome the above-described drawbacks.